SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 218

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

11.5.2
Figure 11-4. Debug Architecture
11.5.3
218
218
data address sampler
SAM3S8/SD8
SAM3S8/SD8
Debug Architecture
Serial Wire/JTAG Debug Port (SWJ-DP)
4 watchpoints
interrupt trace
data sampler
CPU statistics
PC sampler
DWT
low or high level at power up, it must remain in the same state during the duration of the whole
operation.
Figure 11-4
tional units for debug:
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Probes and debugging tool vendors for Cortex M3-based microcontrollers. For further
details on SWJ-DP see the Cortex M3 technical reference manual.
The Cortex-M3 embeds a SWJ-DP Debug port which is the standard CoreSight
combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP),
5 pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
• SWJ-DP (Serial Wire/JTAG Debug Port)
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
shows the Debug Architecture used in the SAM3. The Cortex-M3 embeds four func-
software trace
time stamping
6 breakpoints
32 channels
FPB
ITM
TPIU
SWD/JTAG
SWO trace
SWJ-DP
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
™
debug port. It