SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 877

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

35.6.2
35.6.2.1
Figure 35-3. Functional View of the Channel Block Diagram
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Peripheral Bus
Generator
from APB
Clock
from
z = 0 (x = 0, y = 1),
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)
PWM Channel
Channel Block Diagram
Selector
Clock
2-bit gray
counter z
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies
that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
CAUTION:
Each of the 4 channels is composed of six blocks:
• Before using the PWM macrocell, the programmer must first enable the PWM clock in the
• A clock selector which selects one of the clocks provided by the clock generator (described in
• A counter clocked by the output of the clock selector. This counter is incremented or
Power Management Controller (PMC).
Section 35.6.1 on page
decremented according to the channel configuration and comparators matches. The size of
the counter is 16 bits.
Duty-Cycle
Channel x
Channel 0
Counter
Update
Counter
Period
MUX
Comparator
Comparator
SYNCx
876).
x
y
OCx
OCy
Dead-Time
Dead-Time
Generator
Generator
Channel y (= x+1)
DTOHx
DTOLx
DTOHy
DTOLy
Channel x
Override
Override
Output
Output
OOOHx
OOOLx
OOOHy
OOOLy
SAM3S8/SD8
SAM3S8/SD8
Protection
Protection
Fault
Fault
PWMHx
PWMLx
PWMHy
PWMLy
877
877