SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 89

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.7
4.7.1
ARM DDI 0165B
Data interface
Data interface signals
The ARM9E-S requests data using the data memory interface.
Data transfers take place in the Memory stage of the pipeline. The operation of the data
interface is very similar to the instruction interface.
The signals in the ARM9E-S data bus interface can be grouped into four categories:
•
•
•
•
All memory accesses are conditioned by the state of the memory request signals. You
must not initiate a memory access unless the memory request signals indicate that one
is required. See Data interface cycle types on page 4-24 for more details.
Clocking and clock control signals:
—
—
—
Address class signals:
—
—
—
—
—
—
Memory request signals:
—
—
—
Data timed signals:
—
—
—
Note
Copyright © 2000 ARM Limited. All rights reserved.
CLK
CLKEN
nRESET.
DA[31:0]
DnTRANS
DnRW
DnM[4:0]
DMAS[1:0]
DLOCK.
DnMREQ
DSEQ
DMORE.
WDATA[31:0]
RDATA[31:0]
DABORT.
Memory Interface
4-13