SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 143

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
Scan chain 2
In halt mode debug a request on one of the external debug interface signals, or on an
internal functional unit known as the EmbeddedICE-RT logic, forces the ARM9E-S into
debug state. The events that activate debug are:
•
•
•
•
The internal state of the ARM9E-S is examined using the JTAG serial interface, that
allows instructions to be serially inserted into the core pipeline without using the
external data bus. So, for example, when in debug state, a store multiple (
inserted into the instruction pipeline, and this exports the contents of the ARM9E-S
registers. This data can be serially shifted out without affecting the rest of the system.
a breakpoint (a given instruction fetch)
a watchpoint (a data access)
an external debug request
scanned debug request (a debug request scanned into the EmbeddedICE-RT delay
control register).
EmbeddedICE-RT
Copyright © 2000 ARM Limited. All rights reserved.
ARM9E-S
TAP controller
ARM9E-S
Scan chain 1
Figure 7-2 ARM9E-S block diagram
Debug Interface and EmbeddedICE-RT
ARM9E-S
core
STM
) can be
7-5