SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 216

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

AC Parameters
9.2
9-8
AC timing parameter definitions
Table 9-1 shows target AC parameters. All figures are expressed as percentages of the
CLK period at maximum operating frequency.
Where 0% is given, this indicates the hold time to clock edge plus the maximum clock
skew for internal clock buffering.
Symbol
Tcyc
Tisclken
Tihclken
Tovitrans
Tohitrans
Toviaddr
Tohiaddr
Tovictl
Tohictl
Tisinstr
Tihinstr
Tisiabort
Tihiabort
Tisiebkpt
Tihiebkpt
Tovdtrans
Tohdtrans
Tovdaddr
Note
Copyright © 2000 ARM Limited. All rights reserved.
Parameter
CLK cycle time
CLKEN input setup to rising CLK
CLKEN input hold from rising CLK
Rising CLK to instruction transaction valid
Instruction transaction hold time from rising CLK
Rising CLK to IA valid
IA hold time from rising CLK
Rising CLK to instruction control valid
Instruction control hold time from rising CLK
INSTR input setup to rising CLK
INSTR input hold from rising CLK
IABORT input setup to rising CLK
IABORT input hold from rising CLK
DBGIEBKPT input setup to rising CLK
DBGIEBKPT input hold from rising CLK
Rising CLK to data transaction valid
Data transaction hold time from CLK rising
Rising CLK to DA valid
Table 9-1 Target AC timing parameters
Min
100%
40%
-
-
>0%
-
>0%
>0%
20%
-
15%
-
15%
-
-
>0%
-
-
ARM DDI 0165B
Max
-
-
0%
80%
-
80%
-
80%
-
-
0%
-
0%
-
0%
70%
-
80%