SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 217

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
Symbol
Tohdaddr
Tovdctl
Tohdctl
Tovwdata
Tohwdata
Tisrdata
Tihrdata
Tisdabort
Tihdabort
Tisdewpt
Tihdewpt
Tovintdis
Tohintdis
Tovpass
Tohpass
Tovlate
Tohlate
Tischsd
Tihchsd
Tischse
Tihchse
Tisint
Tihint
Tisnreset
Tihnreset
Copyright © 2000 ARM Limited. All rights reserved.
Parameter
DA hold time from CLK rising
Rising CLK to data control valid
Data control hold time from CLK rising
Rising CLK to WDATA valid
WDATA hold time from CLK rising
RDATA input setup to rising CLK
RDATA input hold from rising CLK
DABORT input setup to rising CLK
DABORT input hold from rising CLK
DBGDEWPT input setup to rising CLK
DBGDEWPT input hold from rising CLK
Rising CLK to Sensitive to interrupt status valid
Sensitive to interrupt status hold from CLK rising
Rising CLK to PASS valid
PASS hold time from CLK rising
Rising CLK to CPLATECANCEL valid
CPLATECANCEL hold from CLK rising
CHSD input setup to rising CLK
CHSD input hold from rising CLK
CHSE input setup to rising CLK
CHSE input hold from rising CLK
Interrupt input setup to rising CLK
Interrupt input hold from rising CLK
nRESET input setup to rising CLK
nRESET input hold from rising CLK
Table 9-1 Target AC timing parameters (continued)
Min
>0%
-
>0%
-
>0%
20%
-
15%
-
15%
-
-
>0%
-
>0%
-
>0%
30%
-
30%
-
15%
-
25%
-
AC Parameters
Max
-
70%
-
20%
-
-
0%
-
0%
-
0%
70%
-
40%
-
25%
-
-
0%
-
0%
-
0%
-
0%
9-9