SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 140

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7.1
7.1.1
7.1.2
7-2
About the debug interface
Halt mode
Monitor mode
The ARM9E-S debug interface is based on IEEE Std. 1149.1-1990, Standard Test
Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation
of the terms used in this chapter and for a description of the TAP controller states.
The ARM9E-S contains hardware extensions for advanced debugging features. These
make it easier to develop application software, operating systems, and the hardware
itself. ARM9E-S supports two modes of debug operation:
•
•
In halt mode debug, the debug extensions allow the core to be forced into debug state.
In debug state, the core is stopped and isolated from the rest of the system. This allows
the internal state of the core, and the external state of the system, to be examined while
all other system activity continues as normal. When debug has been completed, the core
and system state can be restored, and program execution resumed.
On a breakpoint or watchpoint, an Instruction Abort or Data Abort is generated instead
of entering halt mode debug. When used in conjunction with a debug monitor program
activated by the abort exception entry, it is possible to debug the ARM9E-S while
allowing the execution of critical interrupt service routines. The debug monitor program
typically communicates with the debug host over the ARM9E-S debug communication
channel. Monitor mode debug is described in Monitor mode debug on page 7-21.
Halt mode
Monitor mode.
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ARM DDI 0165B