SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 80

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SAM9263

Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9263

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Memory Interface
4.3
4.3.1
4.3.2
4-4
Instruction interface addressing signals
IA[31:1]
ITBIT
The address class signals for the instruction memory interface are:
IA[31:1] is the 31-bit address bus that specifies the address for the transfer. All
addresses are byte addresses, so a burst of 32-bit instruction fetches results in the
address bus incrementing by four for each cycle.
The ARM9E-S does not produce IA[0] as all instruction accesses are halfword-aligned
(that is, IA[0] = 0).
The address bus provides 4GB of linear addressing space. When a word access is
signaled the memory system must ignore IA[1].
The ITBIT signal encodes the size of the instruction fetch. The ARM9E-S can request
word-sized instructions (when in ARM state) or halfword-sized instructions (when in
Thumb state). This is encoded on ITBIT as shown in Table 4-1.
The size of transfer does not change during a burst of S cycles.
IA[31:1]
ITBIT
InTRANS on page 4-5
InM[4:0] on page 4-5.
Note
Copyright © 2000 ARM Limited. All rights reserved.
ITBIT
1
0
Table 4-1 Transfer widths
Transfer width
Halfword
Word
ARM DDI 0165B

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