SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 87

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.6.3
4.6.4
ARM DDI 0165B
Instruction interface, internal cycles
Instruction interface, merged I-S cycles
During an internal cycle, the ARM9E-S does not require an instruction fetch, because
an internal function is being performed, and no useful prefetching can be performed at
the same time.
Where possible the ARM9E-S broadcasts the address for the next access, so that decode
can start, but the memory controller must not commit to a memory access. This is
described further in Instruction interface, merged I-S cycles.
Where possible, the ARM9E-S performs an optimization on the bus to allow extra time
for memory decode. When this happens, the address of the next memory cycle is
broadcast during an internal cycle on this bus. This allows the memory controller to
decode the address, but it must not initiate a memory access during this cycle. In a
merged I-S cycle, the next cycle is a sequential cycle to the same memory location. This
commits to the access, and the memory controller must initiate the memory access. This
is shown in Figure 4-4 on page 4-12.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
InMREQ,
ISEQ
INSTR[31:0]
Address class
signals
Address
N cycle
Figure 4-3 Sequential instruction fetch cycles
N cycle
Address + 4
S cycle
Instruction
data 1
S cycle
Memory Interface
Instruction
data 2
4-11