SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 281

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.13
C.13.1 Breakpoint and watchpoint coupling example
ARM DDI 0165B
Coupling breakpoints and watchpoints
You can couple watchpoint units 1 and 0 together using the CHAIN and RANGE
inputs. Using CHAIN enables Watchpoint 0 to be triggered only if Watchpoint 1 has
previously matched. Using RANGE enables you to perform simple range checking by
combining the outputs of both watchpoints.
Let:
Av[31:0]
Am[31:0]
A[31:0]
Dv[31:0]
Dm[31:0]
D[31:0]
Cv[8:0]
Cm[7:0]
C[9:0]
CHAINOUT signal
The CHAINOUT signal is derived as follows:
WHEN (({Av[31:0],Cv[4,2:0]} XNOR {A[31:0],C[4,2:0]}) OR
{Am[31:0],Cm[4:0]} == 0xFFFFFFFFF)
CHAINOUT = ((({Dv[31:0],Cv[6:4]} XNOR {D[31:0],C[7:5]}) OR
{Dm[31:0],Cm[7:5]}) == 0x7FFFFFFFF)
The CHAINOUT output of Watchpoint register 1 provides the CHAIN input to
Watchpoint 0. This CHAIN input allows for quite complicated configurations of
breakpoints and watchpoints.
There is no CHAIN input to Watchpoint 1 and no CHAIN output from Watchpoint 0.
Note
Copyright © 2000 ARM Limited. All rights reserved.
be the value in the address value register
be the value in the address mask register
be the IA bus from the ARM9E-S if control register bit 3 is clear, or the
DA bus from the ARM9E-S if control register bit 3 is set
be the value in the data value register
be the value in the data mask register
be the INSTR bus from the ARM9E-S if control register bit 3 is clear, or
the RDATA bus from the ARM9E-S if control register bit 3 is set and the
processor is doing a read, or the WDATA bus from the ARM9E-S if
control register bit 3 is set and the processor is doing a write
be the value in the control value register
be the value in the control mask register
be the combined control bus from the ARM9E-S, other watchpoint
registers, and the DBGEXT signal.
Debug in depth
C-41