SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 203

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.25
ARM DDI 0165B
Cycle
ready
not ready
a. IREQ = InMREQ, ISEQ.
b. DREQ = DnMREQ, DSEQ.
c. P = PASS.
d. LC = LATECANCEL.
Coprocessor register transfer (from ARM)
1
1
.
n
n+1
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
The move to coprocessor (
coprocessor register.
Data is transferred over the data bus interface, in a similar fashion to a store register
operation.
An interrupt can cause the ARM9E-S to abandon a busy-waiting coprocessor
instruction (see Busy-waiting and interrupts on page 6-17).
Coprocessor operations are only available in ARM state.
The
MCR
IREQ
S cycle
I cycle
I cycle
I cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction cycle timings are shown in Table 8-32.
a
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
-
-
(pc+3i)
-
MCR
DA
-
-
-
-
-
) operation transfers a specified ARM register to a
DREQ
C cycle
I cycle
C cycle
I cycle
I cycle
b
Table 8-32 MCR instruction cycle timing
WDATA
Rd
-
-
Rd
-
P
1
1
1
1
1
c
LC
0
0
0
0
0
d
Instruction Cycle Times
CHSD
LAST
WAIT
CHSE
-
WAIT
WAIT
LAST
-
8-43