SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 56

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SAM9263

Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9263

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Programmer’s Model
2.7.3
2-14
The relationship between ARM state and Thumb state registers
The Thumb state registers relate to the ARM state registers in the following way:
These relationships are shown in Figure 2-5.
Registers r0–r7 are known as the low registers. Registers r8–r15 are known as the high
registers.
Thumb state r0–r7 and ARM state r0–r7 are identical.
Thumb state CPSR and SPSRs and ARM state CPSR and SPSRs are identical.
Thumb state SP maps onto ARM state r13.
Thumb state LR maps onto ARM state r14.
The Thumb state PC maps onto the ARM state PC (r15).
Program counter (PC)
Note
Copyright © 2000 ARM Limited. All rights reserved.
Stack pointer (SP)
Link register (LR)
Thumb state
Figure 2-5 Mapping of Thumb state registers onto ARM state registers
CPSR
SPSR
r0
r2
r3
r4
r5
r6
r7
r1
Program counter (r15)
Stack pointer (r13)
Link register (r14)
ARM state
CPSR
SPSR
r10
r12
r11
r0
r2
r3
r4
r5
r6
r7
r8
r9
r1
ARM DDI 0165B

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