SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 100

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.10
4-24
Data interface cycle types
The ARM9E-S data interface is pipelined, and so the address class signals and the
memory request signals are broadcast in the bus cycle ahead of the bus cycle to which
they refer. This gives the maximum time for a memory controller to decode the address,
and respond to the access request.
A single memory cycle is shown in Figure 4-8.
The ARM9E-S data interface can perform four different types of memory cycle. These
are indicated by the state of the DnMREQ and DSEQ signals. Memory cycle types are
encoded on the DnMREQ and DSEQ signals as shown in Table 4-15.
DnMREQ
0
0
1
1
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnMREQ,
DSEQ,
DMORE
Address class
signals
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
DSEQ
0
1
0
1
Cycle type
N cycle
S cycle
I cycle
C cycle
Cycle type
Address
Description
Nonsequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer cycle
Figure 4-8 Simple memory cycle
Bus cycle
Write data
Read data
Table 4-15 Cycle types
ARM DDI 0165B