ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 83

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.15
8.16
8.17
32002F–03/2010
Swap instructions
System register instructions
System control instructions
The rete instruction has a latency of 12 cycles when returning from INT0-INT3 modes, 5 cycles
otherwise. The rete instruction can be aborted by a pending interrupt.
Table 8-11.
The swap instruction performs two atomical memory accesses, first one read and then one
write.
Table 8-12.
This group moves data to and from the system registers. Accesses to system registers are per-
formed in the EX stage, taking one cycle.
MTSR to SREG takes 3 cycles, MTSR to all other system registers takes 1 cycle.
Table 8-13.
This group contains simple single-cycle instructions that control the behaviour of different parts
of the system. The frs, pref and sync instructions are executed as NOP in AVR32UC.
Table 8-14.
Mnemonics
retd
rete
rets
retss
Mnemonics
xchg
Mnemonics
mfdr
mfsr
mtdr
mtsr
musfr
mustr
Mnemonics
frs
Return from execution mode instructions
Swap instructions
System register instructions
System control instructions
C
C
C
C
E
E
E
E
E
C
C
C
Operands
Operands
Rd, Rx, Ry
Operands
Rd, SysRegNo
Rd, SysRegNo
SysRegNo, Rs
SysRegNo, Rs
Rs
Rd
Operands
Description
Return from exception
Return from supervisor call
Return from Secure State call. CPU revision 3
and higher only.
Description
Exchange register and memory.
Description
Move debug register to Rd.
Move Rs to system register.
Description
Invalidate the return address stack.
Return from debug mode
Move system register to Rd.
Move Rs to debug register.
Move Rs to status register.
Move status register to Rd.
AVR32
Issue
latency
2
Issue
latency
1
1
1/3
1
1
Issue
latency
1
1
Issue
latency
3
5 / 12
5
5
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