ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 64

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.5
6.6
6.6.1
6.6.2
32002F–03/2010
IRAM Write buffer
Memory barriers
Instruction memory barriers
Data memory barriers
being performed. Refer to the device datasheet for information on any relationships between
CPU and device clock frequencies imposed by the local bus.
The EX stage has a write buffer used to hold data to be written to the IRAM section. The opera-
tion of this buffer is usually transparent to the programmer. The programmer should be aware of
the following:
Memory barriers are constructs used to enfore memory consitency. Caches and self-modifying
code may cause memory to become inconsistent. AVR32UC has a simple pipeline with no
caches, so there is usually no need for memory barriers. Mechanisms for memory barriers are
present to handle the cases where such barriers are needed.
An instruction memory barrier (IMB) is usually only needed when executing self-modifying code,
for example when self-programming program flash. In this case, one must ensure that all levels
in the memory hierarchy are consistent. Due to the simple non-cached memory system in
AVR32UC, this is usually trivial.
The programmer should make sure that an IMB is used if there is a possibility that an instruction
to be modified by self-modifying code has already been prefetched by the instruction prefetch
unit. In this case, an IMB should be inserted between the instruction modifying the code and the
execution of the modified instruction. To make sure that the modified version of the instruction is
executed, the prefetch buffer should be flushed between changing the program memory and
executing the new version of the program.
Any instruction performing a change-of flow, such as return from exception, conditional
branches, unconditional branches, subprogram call or return, or instructions writing to PC would
implement an IMB in AVR32UC.
A data memory barrier (DMB) is used to make sure that a data memory access, either a read or
write, is actually performed before the rest of the code is executed. Caches, write buffers and
• The IRAM has a single port, allowing either one read or one write per clock cycle.
• The write buffer is pipelined, allowing sequential writes to IRAM to be pipelined without any
• Any read instruction to IRAM in EX will be performed immediately, even if a previous store
• If a read instruction in EX accesses the same address as the data in the write buffer is to be
• The contents of the write buffer is written to the physical RAM as soon as the memory
• The state of the write buffer may affect the timing of RMW instructions, see
pipeline stalls. The previous contents of the write buffer is written to the RAM in parallel with
the new store data being placed in the write buffer.
instruction has placed data to store in the write buffer. In this case, the previous store data
remains in the write buffer and will be written back to RAM in a later clock cycle.
stored to, the pipeline is stalled for one clock cycle while the write buffer is emptied to RAM.
The read will be performed normally in the next clock cycle.
interface is not used by any instructions.
write instructions” on page 84
for details
“Read-modify-
AVR32
64