ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 21

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.4
3.4.1
3.4.2
3.4.3
32002F–03/2010
EX pipeline stage
ALU section
Multiply section
Load-store section
The Execute (EX) pipeline stage performs register file reads, operations on registers and mem-
ory, and register file writes.
The ALU pipeline performs most of the data manipulation instructions, like arithmetical and logi-
cal operations. The ALU stage performs the following tasks:
All multiply instructions execute in the multiply section. This section implements a 32 by 32 mul-
tiplier array, and 16x16, 32x16 and 32x32 multiplications and multiply-accumulates therefore
have an issue latency of one cycle. Multiplication of 32 by 32 bits to a 64-bit result require two
iterations through the multiplier array, and therefore needs several cycles to complete. This will
stall the multiply pipeline until the instruction is complete.
A special accumulator cache is implemented in the MUL section. This cache saves the multiply-
accumulate result in dedicated registers in the MUL section, as well as writing them back to the
register file. This allows subsequent MAC instructions to read the accumulator value from the
cache, instead of from the register file. This will speed up MAC operations by one clock cycle. If
a MAC instruction targets a register not found in the cache, one clock cycle is added to the MAC
operation, loading the accumulator value from the register file into the cache. In the next cycle,
the MAC operation is restarted automatically by hardware. If an instruction, like an add, mul or
load, is executed with target address equal to that of a valid cached register, the instruction will
update the cache.
The accumulator cache can hold one doubleword accumulator value, or one word accumulator
value. Hardware ensures that the accumulator cache is kept consistent. If another pipeline sec-
tion writes to one of the registers kept in the accumulator cache, the cache is updated. The
cache is automatically invalidated after reset.
The load-store (LS) pipeline is able to read or write one register per clock cycle. The address is
calculated by the ALU section. Thereafter the address is passed on to the LS section and output
to the memory interface, together with the data to write if the access is a write. If the access is a
read, the read data is returned from the memory interface in the same cycle. If the read data
requires typecasting or other manipulation like performed by ldins or ldswp, this manipulation is
performed in the same cycle.
Any load or store multiple registers are decoded by the ID stage and passed on to the EX stage
as a series of single load or store word operations.
• Target address calculation and condition check for change-of-flow instructions.
• Condition code checking for conditional instructions.
• Address calculation for memory accesses
• Writeback address calculation for the LS pipeline.
• All flag setting for arithmetical and logical instructions.
• The saturation needed by satadd and satsub.
• The operation needed by satrnds, satrndu, sats and satu.
• Signed and unsigned division
AVR32
21