ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 14

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
SR- Status Register
EVBA - Exception Vector Base Address
ACBA - Application Call Base Address
CPUCR - CPU Control Register
Table 2-2.
The Status Register is mapped into the system register space. This allows it to be loaded into
the register file to be modified, or to be stored to memory. The Status Register is described in
detail in
This register contains a pointer to the exception routines. All exception routines start at this
address, or at a defined offset relative to the address. Special alignment requirements may
apply for EVBA, depending on the implementation of the interrupt controller. Exceptions are
described in detail in the AVR32 Architecture Manual.
Pointer to the start of a table of function pointers. Subroutines can thereby be called by the com-
pact acall instruction. This facilitates efficient reuse of code. Keeping this pointer as a register
facilitates multiple function pointer tables. ACBA is a full 32 bit register, but the lowest two bits
should be written to zero, making ACBA word aligned. Failing to do so may result in erroneous
behaviour.
Register controlling the configuration and behaviour of the CPU. The following fields are defined:
Table 2-3.
Reg #
110
111
112-191
192-255
248
249
250
251
252
253
254
255
Name
-
NOCOMP
RES
LOCEN
Section 2.4 ”The Status Register” on page
Bit
Other
17
16
Address
440
444
448-764
768-988
992
996
1000
1004
1008
1012
1016
1020
System Registers (Continued)
CPU control register
Reset
-
0
0
Name
SS_RAR
SS_RSR
Reserved
IMPL
MSU_ADDRHI
MSU_ADDRLO
MSU_LENGTH
MSU_CTRL
MSU_STATUS
MSU_DATA
MSU_TAIL
Reserved
Description
Unused. Read as 0. Should be written as 0.
If set, COUNT is not set on COMPARE match. If cleared, COUNT is
cleared on COMPARE match.
Local Bus Enable. Must be written to 1 to enable the local bus. Any
access attempted to the LOCAL section when this bit is cleared will
result in a BUS ERROR.
Function
Secure State Return Address Register
Secure State Return Status Register
Reserved for future use
IMPLEMENTATION DEFINED
Memory Service Unit Address High Register
Memory Service Unit Address Low Register
Memory Service Unit Length Register
Memory Service Unit Control Register
Memory Service Unit Status Register
Memory Service Unit Data Register
Memory Service Unit TailRegister
Reserved for future use
8.
AVR32
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