ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 7

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2. Programming Model
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
32002F–03/2010
Architectural compatibility
Implementation options
Register file configuration
Memory protection
Java support
Floating-Point Hardware
This chapter describes the programming model and the set of registers accessible to the user. It
also describes the implementation options in AVR32UC.
AVR32UC is fully compatible with the Atmel AVR32A architecture. AVR32UC devices imple-
menting both revision 2 and revision 3 of the AVR32 Architecture exist. Refer to the device
datasheet or the device’s CONFIG0 register to determine which architecture revision the device
implements.
Architecture revision 3 is fully backwards compatible with revision 2, and additionally
implements:
AVR32UC optionally supports an MPU as specified by the AVR32 architecture.
AVR32UC does not implement Java hardware acceleration.
AVR32UC optionally supports Floating-Point Hardware implemented as coprocessor
instructions.
The AVR32A architecture dictates a specific register file implementation, reproduced below.
Secure state context and secure state system registers are only available in devices implement-
ing revision 3 of the AVR32 architecture.
• Secure state with associated programming model
• The automatic clearing of COUNT on COMPARE match is now optional and disabled by
setting the NOCOMPRES bit in CPUCR.
AVR32
7