ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 15

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
ECR - Exception Cause Register
RSR_DBG - Return Status Register for Debug Mode
RAR_DBG - Return Address Register for Debug Mode
CONFIG0 / 1 - Configuration Register 0 / 1
COUNT - Cycle Counter Register
Table 2-3.
This register identifies the cause of the most recently executed exception. This information may
be used to handle exceptions more efficiently in certain operating systems. The register is
updated with a value equal to the EVBA offset of the exception, shifted 2 bit positions to the
right. Only the 9 lowest bits of the EVBA offset are considered. As an example, an ITLB miss
jumps to EVBA+0x50. The ECR will then be loaded with 0x50>>2 == 0x14. The ECR register is
not loaded when an scall, Breakpoint or OCD Stop CPU exception is taken. Note that for inter-
rupts, the offset is given by the autovector provided by the interrupt controller. The resulting ECR
value may therefore overlap with an ECR value used by a regular exception. This can be
avoided by choosing the autovector offsets so that no such overlaps occur.
When Debug mode is entered, the status register contents of the original mode is automatically
saved in this register. When the debug routine is finished, the retd instruction copies the con-
tents of RSR_DBG into SR.
When Debug mode is entered, the Program Counter contents of the original mode is automati-
cally saved in this register. When the debug routine is finished, the retd instruction copies the
contents of RAR_DBG into PC.
Used to describe the processor, its configuration and capabilities. The contents and functionality
of these registers is described in detail in
Can be used as a general counter to time for example execution time. Can also be used
together with COMPARE to implement a periodic interrupt for example for an OS timer. The con-
tents and functionality of this register is described in detail in
COUNT registers” on page
Name
SPL
CPL
COP
SIE
Bit
15:11
10:6
5:1
0
CPU control register
Reset
16
16
8
1
17.
Description
Slave Pending Limit. The maximum number of clock cycles the slave
interface can have a request pending due to the CPU owning the RAMs.
After this period, the CPU will lose arbitrartion for the RAM, and the
slave access can proceed.
CPU Pending Limit. The maximum number of clock cycles the CPU can
have a request pending due to the slave interface owning the RAMs.
After this period, the slave interface will lose arbitrartion for the RAM,
and the CPU access can proceed.
CPU Ownership Period. The number of cycles the CPU is guaranteed
to own the RAM after it has won the arbitration for the RAM. No
arbitration will be performed during this period.
Slave Interface Enable. If this bit is set, the slave interface is enabled.
Otherwise, the slave interface is disabled and any slave access will be
stalled.
Section 2.7 ”Configuration Registers” on page
Section 2.6 ”COMPARE and
AVR32
17.
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