ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 110

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ATUC64L4U

Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC64L4U

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32002F–03/2010
To be able to use JTAG-based debug tools for AVR32 without adapters, it is recommended that
a circuit design using an AVR32 device should use a standard 10-pin 50-mil IDC connector with
the pinout shown in Table 9-16. The signals are described in Table 9-17.
Table 9-16.
Table 9-17.
Signal
TCK
TDO
TMS
N/C
TDI
Pin
TRST_N
TCK
TMS
TDI
TDO
RESET_N
VREF
AVR32 standard JTAG connector pinout. All directions relative to processor
JTAG signals
Direction
Input
Input
Input
Input
Output
Input
Output
Dir
In
Out
In
In
Description
Test Clock. Data is driven on falling edge, sampled on rising edge.
Test Data In
Test Data Out
Device reset
Reference voltage from target. Signals should be driven relative to this
voltage level.
Asynchronous reset for the TAP controller and JTAG registers
Test Mode Select
Pin
1
3
5
7
9
Pin
2
4
6
8
10
Dir
Out
In
Signal
GND
VREF
RESET_N
N/C
N/C
AVR32
110

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