ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 105

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
Table 9-11.
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit Number
23
22
21:20
19:14
13
12
11:9
8
Development Control Register
Field Name
IRP
SQA
EOS
Reserved
DBE
DBR
Reserved
SS
Init. Val.
0
0
0
0
0
0
Description
IRP - Instruction Replace
If IRP is written to one before exiting OCD Mode
with the retd instruction, the first instruction after
exiting OCD Mode will be fetched from the Debug
Instruction Register. This bit is cleared
automatically after this fetch takes place. This bit
will not have any effect if written at the same time
as RES.
SQA - Software Quality Assurance
0: Regular program trace
1: SQA enhanced program trace
EOS - Event Out Select
00 = No operation
01 = Emit event out when the CPU enters Debug
Mode
10 = Emit event out for breakpoints/watchpoints
11 = Emit event out for message insertion into the
TXQ
DBE - Debug Enable
DBE enables Debug Mode and all debug features
in the CPU. DBE must be written to one to enable
breakpoints, debug requests, or single steps.
DBR - Debug Request
Writing DBR to one while DBE is asserted causes
the CPU to enter Debug Mode. If the CPU was in
sleep mode, it will first be woken up before
entering Debug Mode. The DBR bit is cleared
automatically when Debug Mode is entered.
SS - Single Step
If SS is written to one before exiting Debug Mode
with the retd instruction, exactly one instruction will
be executed before returning to Debug Mode. SS
stays one until written to zero by the debugger.
AVR32
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