ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 120

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.4.2.1
9.4.2.2
9.4.2.3
9.4.3
9.4.3.1
32002F–03/2010
Data Breakpoint interface
Program Breakpoints
Watchpoints
Data alignment
Data Breakpoints
The Watchpoint Message Generator (WMG) generates watchpoint messages for all breakpoint
modules and data trace watchpoints.
Optionally, a breakpoint or watchpoint can be signalled by a pulse on the EVTO pin. This
requires DC:EOS bits to be set to 1 and EOC in the corresponding Breakpoint/Watchpoint Con-
trol Register must be written to one.
In order to enable a simple program breakpoint the Breakpoint / Watchpoint Address (BWA) and
Breakpoint / Watchpoint Control (BWC) registers for that breakpoint must be updated.
The BWA register must be written with the address of the instruction where the debugger wants
to halt.
The BWC must have the Breakpoint / Watchpoint Enable (BWE) field set to breakpoint.
Program breakpoints break on the instruction pointed to by BWA. The instruction will cause a
debug exception and the Debug Mode Link Register (RAR_DBG) and Debug Mode Return Sta-
tus Register (RSR_DBG) will point to the instruction that caused the debug exception. The
Development Status register will also be updated to indicate which breakpoint caused the
exception. In OCD Mode the debug tool can then feed the CPU with debug code to ascertain the
state of the processor. In OCD Mode the breakpoint modules are disabled.
Upon return from Debug Mode, the PC and SR will be restored from the RAR_DBG and
RSR_DBG and the instruction that caused the debug exception will be fetched again. If the pro-
gram breakpoint has not been disabled in Debug Mode, the Ignore First Match (IFM) bit in the
Development Control (DC) register must be written to one to avoid triggering another breakpoint
on the first instruction after exiting Debug Mode. The IFM bit prevents any Program Breakpoint
operation on the first instruction after exiting Debug Mode.
When enabled in the BWC, a watchpoint message is sent when the instruction address matches
the address stored in BWA. If both a Trace watchpoint and a Watchpoint triggers at the same
time, the Trace watchpoint will be ignored and only a Watchpoint Hit message will be generated.
Note that Program, Data, and Trace watchpoints are generated at different pipeline stages and
will not be synchronized when the messages are generated. A Program Watchpoint on a load
store instruction will hit before a data watchpoint on the same instruction.
Data Breakpoint modules listen on the data address and data value lines between the CPU and
the data cache and can halt the CPU, or send a watchpoint message, if the address and / or
value meets a stored compare value. Unlike program breakpoints, data breakpoints halt on the
next instruction after the load / store instruction that caused the breakpoint has completed.
The BWA register must be written with the address of the data the debugger wants to halt on.
The AVR32 can read or write data in bytes, halfwords, or words. The same data location can be
accessed through either operation, e.g. a byte location can be accessed as part of a double
word. The data bus operations seen by the OCD system are always aligned, i.e. halfwords start
on halfword boundaries, word accesses start on word boundaries, as illustrated in Figure 9-8. If
AVR32
120