ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 34

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.9.1.16
3.9.1.17
32002F–03/2010
Illegal Opcode
Unimplemented Instruction
This exception is issued when the core fetches an unknown instruction, or when a coprocessor
instruction is not acknowledged. When entering the exception routine, the return address on
stack points to the instruction that caused the exception.
This exception is issued when the core fetches an instruction supported by the instruction set
but not by the current implementation. This allows software implementations of unimplemented
instructions. When entering the exception routine, the return address on stack points to the
instruction that caused the exception.
Table 3-5.
Privileged Instructions
All SIMD instructions
Coprocessor instructions adressing
unimplemented coprocessors
cache - perform cache operation
incjosp - increment Java stack pointer
popjc - pop Java context
pushjc - push Java context
retj- return from Java mode
tlbr - read addressed TLB entry into
TLBEHI and TLBELO
tlbw - write TLB entry registers into
TLB
tlbs - search TLB for entry matching
TLBEHI[VPN]
PC = EVBA | 0x1C;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x20;
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x24;
SYS
SYS
SYS
SYS
List of unimplemented instructions.
) = PC;
) = SR;
) = PC;
) = SR;
Comment
No SIMD implemented
No cache implemented
No Java implemented
No Java implemented
No Java implemented
No Java implemented
No MMU present
No MMU present
No MMU present
AVR32
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