ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 98

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Changing Channel
or Reference
Selection
98
ATtiny26(L)
Figure 54. ADC Timing Diagram, Single Conversion
Figure 55. ADC Timing Diagram, Free Running Conversion
Table 43. ADC Conversion Time
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSR is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
Condition
Extended conversion
Normal conversions
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
Sample & Hold (Cycles from
2
MUX and REFS
Update
Start of Conversion)
Conversion
3
Complete
One Conversion
Sample & Hold
4
11
13.5
1.5
5
12
6
13
7
One Conversion
8
Next Conversion
1
MSB of Result
LSB of Result
9
2
Time (Cycles)
MUX and REFS
Update
10
Conversion
Conversion
Complete
3
11
25
13
12
Sample & Hold
4
13
Conversion
MSB of Result
LSB of Result
Time (µs)
125 - 500
Next Conversion
65 - 260
1
2
MUX and REFS
Update
1477K–AVR–08/10
3