ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 20

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

EEPROM Write During
Power-down Sleep
Mode
Preventing EEPROM
Corruption
I/O Memory
20
ATtiny26(L)
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is
cleared (zero) by hardware, requested data is found in the EEDR Register. The EEPROM read
access takes one instruction and there is no need to poll the EERE bit. When EERE has been
set, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress when new data or address is written to the EEPROM I/O Registers, the write operation
will be interrupted, and the result is undefined.
Table 1. EEPROM Programming Time
Note:
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the write access time has
passed. However, when the write operation is completed, the crystal Oscillator continues run-
ning, and as a consequence, the device does not enter Power-down entirely. It is therefore
recommended to verify that the EEPROM write operation is completed before entering Power-
down.
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using the EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing
instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations
(one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down Sleep mode during periods of low V
Store constants in Flash memory if the ability to change memory contents from software is not
required. Flash memory can not be updated by the CPU, and will not be subject to corruption.
The I/O space definition of the ATtiny26(L) is shown in Table 2
Table 2. ATtiny26(L) I/O Space
Symbol
EEPROM Write (from CPU)
Address Hex
$3D ($5D)
$3F ($5F)
$3B ($5B)
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external Brown-out Reset Protection circuit
can be applied.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the EEPROM Registers from unintentional writes.
1. Uses 1 MHz clock, independent of CKSEL-Fuse settings.
GIMSK
SREG
Name
SP
CC,
the EEPROM data can be corrupted because the supply voltage is
Function
Status Register
Stack Pointer
General Interrupt Mask Register
Number of Calibrated RC
(1)
Oscillator Cycles
8448
(1)
Typical Programming
8.5 ms
Time
CC
. This will pre-
1477K–AVR–08/10