ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 74

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Timer/Counter1
Initialization for
Asynchronous Mode
Timer/Counter1 in
PWM Mode
74
ATtiny26(L)
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK
for Timer/Counter1. After the PLL is enabled, it takes about 64 µs/100 µs (typical/worst case) for
the PLL to lock.
To change Timer/Counter1 to the asynchronous mode, first enable PLL, and poll the PLOCK bit
until it is set, and then set the PCKE bit.
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C –
OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the
PB1(OC1A) and PB3(OC1B) pins. Also inverted, non-overlapping outputs are available on pins
PB0(OC1A) and PB2(OC1B), respectively. The non-overlapping output pairs (OC1A - OC1A
and OC1B - OC1B) are never both set at the same time. This allows driving power switches
directly. The non-overlap time is one prescaled clock cycle, and the high time is one cycle
shorter than the low time.
The non-overlap time is generated by delaying the rising edge, i.e., the positive edge is one
prescaled and one PCK cycle delayed and the negative edge is one PCK cycle delayed in the
asynchronous mode. In the synchronous mode he positive edge is one prescaled and one CK
cycle delayed and the negative edge is one CK cycle delayed. The high time is also one pres-
caled cycle shorter in the both operation modes.
Figure 41. The Non-overlapping Output Pair
When the counter value match the contents of OCR1A and OCR1B, the OC1A and OC1B out-
puts are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the
Timer/Counter1 Control Register A – TCCR1A, as shown in Table 35 below.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the Output
Compare Register (OCR1C), and starting from $00 up again. A compare match with OC1C will
set an Overflow Interrupt Flag (TOV1) after a synchronization delay following the compare
event.
OC1x
OC1x
x = A or B
t
non-overlap
1477K–AVR–08/10