ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 87

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

SPI Slave Operation
Example
1477K–AVR–08/10
The following code demonstrates how to use the USI module as a SPI Master with maximum
speed (fsck = fck/2):
The following code demonstrates how to use the USI module as a SPI slave:
The code is size optimized using only 8 instructions (+ ret). The code example assumes that the
DO is configured as output and SCK pin is configured as input in the DDRB Register. The value
stored in register r16 prior to the function is called is transferred to the master device, and when
the transfer is completed the data received from the master is stored back into the r16 register.
SPITransfer_Fast:
ret
init:
...
SlaveSPITransfer:
SlaveSPITransfer_loop:
out
ldi
ldi
out
out
out
out
out
out
out
out
out
out
out
out
out
out
out
out
in
ldi
out
out
ldi
out
sbis
rjmp
in
ret
USIDR,r16
r16,(1<<USIWM0)+(0<<USICS0)+(1<<USITC)
r17,(1<<USIWM0)+(0<<USICS0)+(1<<USITC)+(1<<USICLK)
USICR,r16 ; MSB
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16 ; LSB
USICR,r17
r16,USIDR
r16,(1<<USIWM0)+(1<<USICS1)
USICR,r16
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
USISR,USIOIF
SlaveSPITransfer_loop
r16,USIDR
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