ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 7

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

AVR CPU Core
Architectural
Overview
1477K–AVR–08/10
The fast-access Register File concept contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This means that during one single clock cycle, one ALU (Arith-
metic Logic Unit) operation is executed. Two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These pointers
are called the X-, Y-, and Z-pointers, and they can address the Register File and the Flash pro-
gram memory.
Figure 2. The ATtiny26(L) AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a
register. Single register operations are also executed in the ALU. Figure 2 shows the
ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register opera-
tion, the conventional memory addressing modes can be used on the Register File as well. This
is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses
($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory can be
accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.
The AVR uses a Harvard architecture concept with separate memories and buses for program
and data memories. The program memory is accessed with a two stage pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
Control Lines
Instruction
1024 x 16
Instruction
Program
Register
Decoder
FLASH
Program
Counter
EEPROM
Registers
128 byte
128 x 8
and Test
Purpose
General
SRAM
8-bit Data Bus
Status
32 x 8
ALU
Serial Interface
Timer/Counter
Comparator
Registers
Watchdog
Universal
2 x 8-bit
Interrupt
ISP Unit
I/O Lines
Control
Analog
ADC
Timer
Unit
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