ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 18

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

EEPROM Data
Memory
EEPROM Read/Write
Access
EEPROM Address
Register – EEAR
18
ATtiny26(L)
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement mode fea-
tures a 63 address locations reach from the base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data
SRAM in the ATtiny26(L) are all accessible through all these addressing modes.
See “Program and Data Addressing Modes” on page 11 for a detailed description of the different
addressing modes.
The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written (see “Memory Programming” on page
107). The EEPROM has an endurance of at least 100,000 write/erase cycles per location.
The EEPROM Access Registers are accessible in the I/O space.
The write access time is typically 8.3 ms. A self-timing function lets the user software detect
when the next byte can be written. A special EEPROM Ready Interrupt can be set to trigger
when the EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed.
• Bit 7 – RES: Reserved Bits
This bit are reserved bit in the ATtiny26(L) and will always read as zero.
• Bit 6..0 – EEAR6..0: EEPROM Address
The EEPROM Address Register – EEAR – specifies the EEPROM address in the 128 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. The ini-
tial value of EEAR is undefined. A proper value must be written before the EEPROM may be
accessed.
Bit
$1E ($3E)
Read/Write
Initial Value
R
7
–
0
EEAR6
R/W
X
6
EEAR5
R/W
X
5
EEAR4
R/W
X
4
EEAR3
R/W
X
3
EEAR2
R/W
X
2
EEAR1
R/W
X
1
EEAR0
R/W
X
0
EEAR
1477K–AVR–08/10