ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 101

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

ADC Multiplexer
Selection Register –
ADMUX
1477K–AVR–08/10
• Bit 7, 6 – REFS1, REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 45. If these bits are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSR is set). The user should disregard the first conversion result after changing
these bits to obtain maximum accuracy. If differential channels are used, using AVCC or an
external AREF higher than (AVCC - 0.2V) is not recommended, as this will affect ADC accuracy.
The internal voltage reference may not be used if an external reference voltage is being applied
to the AREF pin.
Table 45. Voltage Reference Selections for ADC
•
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongo-
ing conversions. For a complete description of this bit, see “ADC Data Register – ADCL and
ADCH” on page 104.
• Bits 4..0 – MUX4..MUX0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See Table 46 for details. If these bits
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSR is set).
Bit
$07 ($27)
Read/Write
Initial Value
REFS1
Bit 5 – ADLAR: ADC Left Adjust Result
0
0
1
1
REFS0
0
1
0
1
REFS1
R/W
7
0
Voltage Reference Selection
AVCC
AREF (PA3), Internal Vref turned off.
Internal Voltage Reference (2.56 V), AREF pin (PA3) not connected.
Internal Voltage Reference (2.56 V) with external capacitor at AREF pin
(PA3).
REFS0
R/W
6
0
ADLAR
R/W
5
0
MUX4
R/W
4
0
MUX3
R/W
3
0
MUX2
R/W
2
0
MUX1
R/W
1
0
MUX0
R/W
0
0
ADMUX
101