NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 39

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Reduced ROT Readout Mode
load.
the pixel output to the column amplifier and parasitic caps
of the 1695 pixels connected to it. 2) The column amplifier
current source transistors. In normal ROT mode, both the
structures are on and to transfer the charge from the pixel to
the column amplifiers, each column amplifier must draw a
larger current.
source is turned off/disabled. The capacitance of the column
itself acts like the sampling capacitor and the capacitance
seen by the pixel is reduced. As a result, the transfer of the
charge is faster and a reduced ROT can be used. In reduced
ROT mode, the dynamic range of the pixel is lesser than in
normal ROT mode but the power consumption is also
reduced.
ROT of nine sensor clock periods (175 ns).
FOT and ROT Pin Timing
internal FOT and ROT periods.
Asynchronous Reset
register, RESET_N_SEQ. Both are active low.
are reset when this pin is low. This includes the sequencer,
the SPI register, and X and Y shift registers. The reset is
asynchronous.
low only resets the sequencer. This is used to restart the
sequencer with the current SPI settings.
Reset on Startup
supply voltages are stable. After the rising edge of
When a row is selected, each pixel sees a large capacitive
This comes from two sections - 1) metal line connecting
In the reduced ROT mode, the column amplifier current
The sensor operates in reduced ROT by default, with a
The chip has two pins (FOT and ROT) that indicate
The sensor has a reset pin, RESET_N, and a reset SPI
RESET_N is the chip reset. All components on the chip
RESET_N_SEQ is the sequencer reset. Bringing this bit
When the sensor starts up, RESET_N is kept low until all
SEN_CLK
ROT pin
SEN_CLK
sync_x
FOT pin
clk_y
vmem
clk_y
actual FOT (FOT_TIMER * 4 SEN_CLK)
actual ROT (ROT_TIMER + 2 SEN_CLK)
Figure 32. ROT Pin Timing
Figure 31. FOT Pin Timing
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39
FOT Pin
VMEM signal to the rising edge of the first internal CLK_Y.
After this rising edge of CLK_Y, the first ROT starts. The
FOT pin goes high at the same moment VMEM goes low
and remains high until one sensor clock period (CLKIN/4)
before the end of the actual FOT. This is shown in Figure 31.
ROT Pin
CLK_Y signal to the falling edge of the internal SYNC_X
signal. The ROT pin goes high at the rising edge of CLK_Y
and remains high until one sensor clock (CLKIN/4) before
the end of the actual ROT.
RESET_N, RESET_N_SEQ is kept low for an additional
0.5 ms.
channels and sync channel) is invalid. When the chip comes
out of reset, but the sequencer is kept in reset, the LVDS
outputs toggle between the idle words.
(100 ns), the pixel array is not completely reset. Information
from the previous integration cycle is still present on the
photodiode. Ensure that the pixels are in reset for at least 3 ms
by keeping RESET_N_SEQ low for a long time, or by not
starting exposure before 3 ms after RESET_N_SEQ.
Table 50. FOT AND ROT PIN TIMING
ROT
FOT
The actual FOT goes from the falling edge of the internal
The actual ROT goes from the rising edge of the internal
Pin
During the chip reset the data on the LVDS outputs (data
If RESET_N_SEQ is only low for a short period of time
Delay vs. Sensor Clock
2.5 ns
2.5 ns
1 SEN_CLK
1 SEN_CLK
Rise and Fall Times
(20 pF Load)
6 ns
6 ns