NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 28

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADC and LVDS Channel Powerdown Registers (b1000010-
1000110 / d66-70)
channels are individually powered down by setting the
appropriate bits of these registers. Powering down a channel
stops the clock for the odd and even ADCs and LVDS
serializer, and turns off the LVDS output driver. Note that the
enable pwd_ena in register d71 is set for these bits to take
affect. Bits 31:0 are used for data channels 31:0 respectively.
Setting bit 33 powers down the output clock channel; bit 32
powers down the sync channel. Setting a particular bit high
brings the selected channel to its power down mode.
Misc1 SuperBlk Control Register (b1000111 / d71)
control and test enable bits. The superblk refers to the AFE,
ADC, CRC, Serialization, and LVDS channels and
supporting controls.
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Table 42. PWD_CHAN<33:0>
Value bit<x>
Each of the 32 data channels, sync, and clock out LVDS
The misc1 superblk control register contains several
crc_en, bit <0>. This bit enables inserting CRC words
into the data channels at the end of a row of image data.
Protocol Layer on page 12 contains more details on this
protocol.
crc_sync_en, bit<1>: This bit enables inserting CRC
words into the sync channel. This is generally not
desired.
pwd_ena, bit<2>. This bit provides the ability to
power down individual channels through the pwd_chan
registers.
pwd_glob, bit<3>. This bit, when set, globally powers
down all 32 data channels, the sync channel, and the
clock out channel. This overrides the per channel power
down controls.
test_en, bit<4>. This bit is provided to test the serial
LVDS output drivers. When set, the LVDS output clock
is routed to all output data channels. This is intended
for debug and testing only.
atst_en, bit<5>. This bit enables driving an external
analog input voltage to the 64 ADCs for testing. When
set, the external pin Analog_in and Vdark reference are
sent to all ADCs.
sblk_spare1, bit<6>. This bit is a spare control bit. It is
set to 0 at POR.
sblk_spare2, bit<7>.: This bit is a spare control bit. It
is set to 1 at POR.
On startup
0
1
Normal operation
Channel powered down
0
Effect
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Table 43. MISC1 SUPERBLK CONTROL REGISTER
crc_en, bit <0>
0
1
On startup
crc_sync_en, bit<1>
0
1
On startup
pwd_ena, bit<2>
0
1
On startup
pwd_glob, bit<3>
0
1
On startup
test_en, bit<4>
0
1
On startup
atst_en, bit<5>
0
1
On startup
sblk_spare1, bit<6>
0
1
On startup
sblk_spare2, bit<7>
0
1
On startup
Value
No CRC words inserted
CRC words inserted into the data stream
Normal operation
1
No CRC words inserted
Normal operation
Crc words inserted into the sync channel
0
Per channel power down disabled
Normal operation
Enable per channel power down
0
Normal operation
Power down all channels
0
Normal operation
Test Mode
0
Normal operation
ADC analog test mode
0
Normal operation
0
Normal operation
1
Effect