NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 37

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

is interrupted after the completion of the current line’s readout (line x in Figure 27).
Dual Slope Integration Timing
integration is controlled through the EXPOSURE_2 pin. If
the dual slope enable bit is set low, the dual slope integration
is disabled. Figure 28 shows the timing. The pix_reset signal
is controlled by the EXPOSURE_1 pin. When pix_reset
goes low, the dual slope reset of the pixel array is activated.
Bringing the EXPOSURE_2 pin high starts the dual slope
integration. The start of FOT is controlled by the falling edge
Readout Modes
modes: training, test image readout, and normal readout.
These modes enable correct communication between the
sensor and the customer system.
Readout of Training Sequence
all data channels and the sync channel transmit alternating
the Idle_A and Idle_B word. Rotating the received Idle_A
and Idle_B words in the receiver allows correcting for skew
between the LVDS outputs and the receiver clock. You can
program the Idle_A and Idle_B words.
.FOT starts before readout. When the EXPOSURE_1 signal goes low before the window readout has finished, the readout
If the dual slope enable bit is set high, dual slope
The sensor is configured to operate in three readout
By setting the TRAINING_EN and BYPASS_MODE bit,
EXPOSURE_1
EXPOSURE_2
EXPOSURE_1
pix_reset_ds
pix_sample
pix_sample
pix_vmem
pix_reset
pix_vmem
pix_reset
DATA
DATA
FOT
FOT
FOT
Figure 28. Dual Slope Integration Timing
Figure 27. High Level Readout Timing
L1
L1
wait till ROT
L2
http://onsemi.com
L2
L3
wait till ROT
37
L3
wait till ROT
of the EXPOSURE_1 pin. The EXPOSURE_2 pin must be
brought low during FOT to be ready for the next cycle.
Setup and Hold Requirements
two chained flipflops that clock on the sensor clock. As a
result, there is no setup requirement for both signals relative
to LVDS_CLKIN. The hold requirement is 15 clock periods
of LVDS_CLKIN.
Readout of Test Image
TRAINING_EN bit low, the sensor is configured to output
a programmable test pattern.
enables frame and line synchronization. Every data channel
transmits a fixed, programmable word to replace normal
data words coming from the ADC. In this mode, the sensor
behaves as in normal readout. The sync channel transmits
programmable keywords to allow frame and line
synchronization. When not transmitting data from the ADC,
the data channels transmit the toggling Idle_A and Idle_B
words. As a result, the data stream from the sensor has a
fixed format.
L4
EXPOSURE_1 and EXPOSURE_2 are deglitched using
By setting the BYPASS_MODE bit high and the
The sync channel operates as in normal readout and
integration time
L x-1
integration time
L
DS integration time
x
L
x
wait till ROT
FOT
L1