NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 13

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Block
stage + ADCs) and the LVDS interface. It multiplexes the
outputs of two ADCs to one LVDS block and performs some
minor data handling:
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LVDS
low noise coupling. It also offers low EMI emissions that are
essential for the high data readout rates that are required by
the LUPA3000 image sensor. LVDS voltage swings range
from 250 mV to 450 mV with a typical of 350 mV. Because
of the low voltage swings, rise and fall times are reduced,
enabling higher operating speeds than CMOS, TTL, or other
drivers operating at the same slew rate. It uses a common
mode voltage ~1.2 V to 1.25 V above ground, and as a result
is more independent of the power supply level and less
susceptible to noise. Differential transmission also reduces
EMI levels. The 2-pin differential output drives a cable with
approximately 100 W characteristic impedance, which is
‘far-end’ terminated with 100 W.
LVDS Data Channels
at a double data rate (DDR) of 412 Mb per second (typical)
using a 206-MHz input clock. The LVDS data channels have
a high speed parallel to the serial converter logic function
(serializer) that serializes the 52 MSPS 8-bit parallel data
from a time multiplexed odd and even kernel ADC pair. The
high-speed serial bit stream drives a LVDS output driver.
The data block is positioned in between the AFE (output
LUPA3000 uses LVDS I/O. LVDS offers low power and
LUPA3000 has 32 LVDS data output channels operating
Calculate and insert CRC
Generate training and test pattern
Figure 12. Interaction of the Data Block with ADC and LVDS
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level calibration.
data output channels. One additional channel generates the
synchronization protocol. A high level overview is
illustrated in Figure 12.
through a 2-pin differential output to represent a logical 1
and logical 0 state respectively. The driver is designed in
compliance with the ANSI/TIA/EIA-644-A-2001 standard.
The circuit consists of a programmable current sink that
defines the drive current, a dynamically controlled current
source, a 4-transistor bridge that steers these currents to the
differential outputs, and a common mode feedback circuit to
balance the sink and source currents.
2.5 mA to 4.5 mA. The termination resistance is specified
from 90 W to 132 W. To allow flexibility in power
consumption, the output drive current is programmed
through the SPI register interface. Settings are available for
operation outside the specified ANSI standard to allow
custom settings for power and speed enhancements. These
settings may require the use of nonstandard termination
resistance. Current drive programming is accomplished
using bits 3:0 of SPI register 72 (decimal – LVDS trim).
Figure 13 on page 14 defines the programmable LVDS
output current settings.
It also contains a huge part of the functionality for black
A number of data blocks are placed in parallel to serve all
The LVDS driver must deliver positive or negative current
The LVDS standard defines the drive current between