NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 14

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LVDS Sync Channel
sensor synchronization control words such as start of frame
(SOF), start of line (SOL), end of line (EOL), idle words
(IdleA and IdleB), and the sensor line address.
receives its input directly from the image core sequencer. An
additional synchronization control logic block ensures
proper data alignment of the synchronization codes to
account for the latency incurred in the other 32 data channels
(due to AFE and ADC signal processing). The LVDS output
driver is similar to that used in other data channel outputs.
LVDS Clk (Clock) Output
This channel provides an output clock that is in phase and
aligned with the data bit stream of the 32 data channels. It is
required for clock and data recovery by the system
processing circuits.
differential CMOS serializer clock, after processing through
the clock distribution buffer network that provides clocks to
all LUPA3000 data channels. The group delay of the output
clock and data channels is ~2.5 ns relative to the incoming
master clock. The LVDS output driver is similar to that used
in other data channel outputs.
LVDS CLK (Clock) Input
master input clock. The input clock rate is typically
206 MHz and also complies with the ANSI LVDS receiver
standards. The input clock drives the internal clock
generator circuit that produces the required internal clocks
for image core and sequencer, AFE and ADCs, CRC
insertion logic, and serializers. LUPA3000 requires the
LUPA3000 includes a LVDS output channel to encode
This channel includes a serializer logic section, but
The LUPA3000 provides a LVDS clock output channel.
A serializer logic section is connected to accept the
LUPA3000 includes a differential LVDS receiver for the
REG 72 < 3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Figure 13. LVDS Driver Programmable Drive Current Settings
I OUT [mA]
1.26
1.68
2.52
2.94
3.36
3.78
4.62
5.04
5.46
5.88
6.72
7.14
7.56
2.1
4.2
6.3
http://onsemi.com
RT[Ω]
72.97
68.75
68.75
68.75
100
100
100
100
100
100
100
100
50
50
50
50
14
following internal clock domains (all internal clock domains
are 2.5 V CMOS levels):
•
•
•
•
•
•
networks to ensure equal group delays and maintain less
than 100 ps maximum channel to channel clock variation.
domains of image sensor core and sequencer. This
adjustment optimizes the data acquisition handshaking
between the image sensor core and the digitization and
serialization channels. SPI register 65 (decimal) controls
delay (or advance) adjustments for these two clocks. For
each of these two imager clocks, 15 adjustments settings are
provided. Each setting allows adjustment for 1/(2x master
clock) adjustment. For example, if the master input clock
runs at 206 MHz, 1/412 MHz = 2.41 ns adjustment
resolution is possible. Refer to Sensor Clock Edge Adjust
Register (b1000001 / d65) on page 26 for programming
details.
programmable delay. These settings allow correct
All clock domains are designed with identical clock buffer
Programmable delay adjustment is provided for the clock
ON Semiconductor provides default settings for the
Serializer clock = 1x differential version of the input
clock (206 MHz typical)
CRC clock = 1/4x the input clock (51.5 MHz typical)
Load pulse = 1/4 (the input clock)at 12.5% duty cycle
version of the input clock: for load and handshake
between CRC parallel data to serializer
ADC and AFE clock = 1/8x the input clock
(25.75 MHz typical)
Sensor clock = 1/4x the input clock (51.5 MHz typical)
with programmable delay
ADC clock =1/8x the input clock (25.75 MHz typical)
with programmable delay
V
OUT [mV]
126
168
210
252
294
336
378
420
337
347
375
404
315
336
357
378
Co mment s
Interconnect capacitance
to accommodate high
Extra drive current
Low power range
Standard range