NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 16

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1. The V
2. The driver output swing is tuned through the LVDS driver bias current settings in the SPI register. This feature is also used to reduce power
3. Jitter with reference to LUPA3000 input clock
4. This is from LVDS point of view, from sensor point of view f
LUPA3000 interface. Use controlled impedance traces to
match trace impedance to the transmission medium. The
best practice regarding noise coupling and reflections is to
run the differential pairs close together. Limit skew due to
Table 12. LVDS DRIVER SPECIFICATIONS
Table 13. LVDS RECEIVER SPECIFICATIONS
|V
|V
V
d|V
I
I
t
|V
d|V
ZT
ZC(f)
I
t
t
t
t
t
t
f
f
I
I
Z
|V
V
T
SA
SAB
r
OFF
SKD1
SKD2
SKCD1
SKCD2
jit_rms
jit_det
MAX
MIN
IA
IA
Output trace characteristics affect the performance of the
T
JIT_TOT
OS
IH
t
ring
consumption. Alternatively, decrease the termination resistor to boost the speed and keep the swing identical by increasing the bias current.
starts influencing the image quality.
T
T
ID
, I
-I
f
Parameter
Parameter
| (Note 1)
(1)|–|V
/I
OS
OS
, V
IB
|
IB
SB
(Note 4)
|
|
|
(Note 3)
IL
(Note 2)
MEM_L
T
(0)|
power supply should have a sourcing and sinking current capability.
Differential logic voltage
Delta differential voltage
Common mode offset
Difference in common mode voltage for logic 1 and 0
Output currents in short to ground condition
Output current in differential short condition
Differential rise and fall time
Differential over and undershoot
Dynamic common mode offset
Termination resistance
Characteristic impedance of the interconnect
Offstate current
Differential skew
Differential channel to channel skew
Differential clock out to data skew
Differential clock in to data skew
Random jitter
Deterministic jitter
Maximum operating frequency
Minimum operating frequency
Input current
Input current unbalance
Required external termination
Differential input
Minimum and maximum input voltages
Total jitter at LUPA3000 clock input
Description
Description
http://onsemi.com
MIN
is 4 MHz (about 10 fps). At lower speeds dark current and storage node leakage
16
receiver end limitations and for reasons of EMI reduction.
Matching the differential traces is very important. Common
mode and interconnect media specifications are identical to
LVDS receiver specifications.
Specification (guaranteed by design)
Specification (guaranteed by design)
Min
100
1.125
90
–
–
0
–
Min
247
400
90
90
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
Typ
100
–
–
–
–
–
1.25
Typ
350
100
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
132
600
500
0.2*V
2.4
1.375
20
6
Max
0.25
454
250
150
132
132
500
206
0.5
50
50
24
12
10
50
1
3
–
T
Units
mV
Units
mV
MHz
MHz
mA
mA
ps
mV
mV
mV
mA
mA
W
mA
V
ps
ns
ns
ns
ns
ps
ps
W
W
V
V
PP