NOIL1SN3000A-GDC ON Semiconductor, NOIL1SN3000A-GDC Datasheet - Page 29

• Manufacturer Part Number: NOIL1SN3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SN3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LVDS Output Current Adjust Register (b1001000 / d72)
control register. The startup value is b0110 that represents
3.76 mA, reflecting the typical LVDS operating point. There
are 16 programmable values available. For more
information, see the section LVDS Data Channels on
page 13.
Programmable Gain Register (b1001001 / d73)
1x–4x in eight steps. This is used with the vref_trim register
to match the ADC dynamic range to the pixel voltage range.
The startup value for this register is b000, which
corresponds to a unity gain (1x). See Programmable Gain
Amplifiers (PGA) on page 9 for information on the control
bit to gain setting table relationship.
Misc2 SuperBlk Control Register (b1001010 / d74)
analog bias and reference controls. The bits are defined in
this section.
•
•
•
•
•
•
•
•
The LVDS output drive current is adjusted with this
The amount of analog gain (in the AFE) is adjusted from
The misc2 superblk control register contains additional
bg_disable, bit <0>: This bit is provided if the on-chip
bandgap needs to be disabled.
int_res, bit<1>: This bit controls whether an on-chip or
external resister is used in setting the bandgap voltage.
pwd_bg, bit<2>: This bit is provided to power down the
bandgap. It is intended for test and debug only.
pwd_vdark, bit<3>: This bit is provided to power down
the driver for the dark reference voltage. It is intended
for test and debug only.
pwd_vref, bit<4>: This bit is provided to power down
the voltage references, vrefp and vrefm. It is intended
for test and debug only.
pwd_vcm, bit<5>: This bit is fixed to ‘1’. See Table 44.
sblk_spare3, bit<6>: This bit is a spare control bit. It is
set to ‘0’ at POR.
sblk_spare4, bit<7>: This bit is a spare control bit. It is
set to ‘1’ at POR.
http://onsemi.com
29
Table 44. MISC2 SUPERBLK CONTROL REGISTER
bg_disable, bit <0>
int_res, bit<1>
pwd_bg, bit<2>
pwd_vdark, bit<3>
pwd_vref, bit<4>
pwd_vcm, bit<5>
sblk_spare3, bit<6>
sblk_spare4, bit<7>
On startup
On startup
On startup
On startup
On startup
On startup
On startup
On startup
Value
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
On-chip bandgap enabled
Normal operation
On-chip bandgap disabled
0
External resistor used in Normal operation
On-chip resister used
0
Normal operation
Bandgap powered down
0
Normal operation
Power down vdark buffer
0
Normal operation
Power down vrefp/vrefm references
0
Disable on-chip VCM generation. Apply
0.9 V to Vcm pin 87 and decouple to
ground with 10 nF capacitor.
1
Normal operation
0
Normal operation
1
Effect