MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 97

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

8.4.1 Crystal Oscillator Circuit
8.5 CGM I/O Signals
8.5.1 External Filter Capacitor Pin (CGMXFC)
8.5.2 PLL Analog Power Pin (VDDA)
8.5.3 PLL Analog Ground Pin (VSSA)
MC68HC908LD60
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 1.1
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The OSCXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. OSCXCLK is then buffered
to produce OSCRCLK, the PLL reference clock. (See
Oscillator
The following paragraphs describe the CGM I/O signals.
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor (C
To prevent noise problems, C
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C
VDDA is the power pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the VDD pin.
VSSA is the ground pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the VSS pin.
Route VDDA and VSSA carefully for maximum noise immunity and
place bypass capacitors as close as possible to the package.
Clock Generator Module (CGM)
(OSC).)
F
should be placed as close to the
F
connection.
F
) is connected to this pin.
Clock Generator Module (CGM)
Section 7.
CGM I/O Signals
Technical Data
97