MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 113

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

9.4.2 Active Resets from Internal Sources
MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1
SIM module in HC08 has the capability to drive the RST pin low when
internal reset events occur.
All internal reset sources actively pull the RST pin low for 32 OSCXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles
5. Internal Reset
address, illegal opcode, COP timeout, or POR
of Internal
4096 OSCXCLK cycles during which the SIM forces the RST pin low.
The internal reset signal then follows the sequence from the falling edge
of RST shown in
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
OSCXCLK
OSCOUT
IRST
RST
RST
IAB
IAB
System Integration Module (SIM)
PC
Reset). Note that for POR resets, the SIM cycles through
Figure 9-6. Sources of Internal Reset
Figure
Figure 9-4. External Reset Timing
ILLEGAL ADDRESS RST
Timing). An internal reset can be caused by an illegal
RST PULLED LOW BY MCU
Figure 9-5. Internal Reset Timing
ILLEGAL OPCODE RST
9-5.
COPRST
32 CYCLES
POR
LVI
INTERNAL RESET
System Integration Module (SIM)
VECT H VECT L
32 CYCLES
(see Figure 9-6. Sources
Reset and System Initialization
(see Figure 9-
VECTOR HIGH
Technical Data
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