MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 245

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

17.6.2 Data Direction Register D
MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1
Address:
HOUT— Sync Processor HOUT Pulse Output Pin
VOUT — Sync Processor VOUT Pulse Output Pin
DE — Sync Processor DE Pulse Output Pin
DCLK — Sync Processor DCLK Pulse Output Pin
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Reset:
Read:
Write:
The PTD3/HOUT pin is the sync processor HOUT pulse output pin.
When the HOUTE bit in the port D control register (PDCR) is clear,
the PTD3/HOUT pin is available for general-purpose I/O. (See
Port D
The PTD2/VOUT pin is the sync processor VOUT pulse output pin.
When the VOUTE bit in the port D control register (PDCR) is clear, the
PTD2/VOUT pin is available for general-purpose I/O. (See
Port D
The PTD1/DE pin is the sync processor DE pulse output pin. When
the DEE bit in the port D control register (PDCR) is clear, the
PTD1/DE pin is available for general-purpose I/O. (See
Options.)
The PTD0/DCLK pin is the sync processor DCLK pulse output pin.
When the DCLKE bit in the port D control register (PDCR) is clear, the
PTD0/DCLK pin is available for general-purpose I/O. (See
Port D
DDRD7
$0007
Bit 7
Figure 17-14. Data Direction Register D (DDRD)
0
Options.)
Options.)
Options.)
Input/Output (I/O) Ports
DDRD6
6
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
DDRD2
2
0
Input/Output (I/O) Ports
DDRD1
17.6.3 Port D
1
0
Technical Data
17.6.3
17.6.3
17.6.3
DDRD0
Bit 0
Port D
0
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