MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 220

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Sync Processor
Technical Data
220
VEDGE — VSync Interrupt Edge Select
VSIF — VSync Interrupt Flag
COMP — Composite Sync Input Enable
VINVO — VOUT Signal Polarity
HINVO — HOUT Signal Polarity
This bit specifies the triggering edge of Vsync interrupt. When it is "0",
the rising edge of internal Vsync signal which is either from the
VSYNC pin or extracted from the composite input signal will set VSIF
flag. When it is "1", the falling edge of internal Vsync signal will set
VSIF flag. Reset clears this bit.
This flag is only set by the specified edge of the internal Vsync signal,
which is either from the VSYNC input pin or extracted from the
composite sync input signal. The triggering edge is specified by the
VEDGE bit. VSIF generates an interrupt request to the CPU if the
VSIE bit is also set. This bit is cleared by writing a "0" to it or by a reset.
This bit is set to enable the separator circuit which extracts the Vsync
pulse from the composite sync input on HSYNC or SOG pin (select by
SOGSEL bit). The extracted Vsync signal is used as it were from the
VSYNC input. Reset clears this bit.
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the VOUT signal (see
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the HOUT signal (see
1 = VSIF bit will be set by rising edge of Vsync
0 = VSIF bit will be set by falling edge of Vsync
1 = A valid edge is detected on the Vsync
0 = No valid Vsync is detected
1 = Composite Sync Input Enabled
0 = Composite Sync Input Disabled
Sync Processor
Table
Table
16-4).
16-4).
MC68HC908LD60
Freescale Semiconductor
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Rev. 1.1