MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 174

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Analog-to-Digital Converter (ADC)
13.4.1 ADC Port I/O Pins
13.4.2 Voltage Conversion
13.4.3 Conversion Time
Technical Data
174
NOTE:
PTC5/ADC5–PTC0/ADC0 are general-purpose I/O pins that are shared
with the ADC channels. The channel select bits, ADCH[4:0], in the ADC
status and control register define which ADC channel/port pin will be
used as the input signal. The ADC overrides the port I/O logic by forcing
that pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
When the input voltage to the ADC equals to VRH, the ADC converts the
signal to $FF (full scale). If the input voltage equals to VRL, the ADC
converts it to $00. Input voltages between VRH and VRL is a straight-line
linear conversion. All other input voltages will result in $FF if greater than
VRH and $00 if less than VRL.
Input voltage should not exceed the analog supply voltages.
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1MHz, then one conversion will take 16µs to complete.
With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz.
Number of bus cycles = conversion time × bus frequency
Analog-to-Digital Converter (ADC)
Conversion time =
16 to17 ADC cycles
ADC frequency
MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1