MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 177

MC68HC908LD60IFU

Manufacturer Part Number
MC68HC908LD60IFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC908LD60IFU

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
6MHz
Program Memory Type
Flash
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
39
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
6-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908LD60IFU
Manufacturer:
FREESCALE
Quantity:
840
13.8 I/O Registers
13.8.1 ADC Status and Control Register
MC68HC908LD60
Freescale Semiconductor
Rev. 1.1
Address:
Three I/O registers control and monitor ADC operation:
Function of the ADC status and control register is described here.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
Reset:
Read:
Write:
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written, or whenever the ADC
data register is read. Reset clears this bit.
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status and control register is written. Reset clears the
AIEN bit.
Figure 13-3. ADC Status and Control Register (ADSCR)
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC input clock register (ADICLK)
$003B
COCO
Bit 7
Analog-to-Digital Converter (ADC)
0
= Unimplemented
AIEN
6
0
ADCO
5
0
ADCH4
4
1
ADCH3
3
1
Analog-to-Digital Converter (ADC)
ADCH2
2
1
ADCH1
1
1
Technical Data
I/O Registers
ADCH0
Bit 0
1
177

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