MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 229

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

16.7 System Operation
MC68HC908LD60
Freescale Semiconductor
HVOCR[1:0]
00
01
10
11
Table 16-9. Free-Running HSOUT, VSOUT, DE, and DCLK Settings
MUL[7:4]
—
3
5
8
9
Rev. 1.1
DCLKPH[1:0] — DCLK Output Phase Adjustment
HVOCR[1:0] — Free Running Video Mode Select Bits
This Sync Processor is designed to assist in determining the video mode
of incoming HSYNC and VSYNC of various frequencies and polarities,
and DPMS modes. In the DPMS standard, a no sync pulses definition
can be detected when the value of the Hsync Frequency Register (the
number of Hsync pulses) is less than one or when the VOF bit is set.
Since the Hsync Frequency Register is updated repeatedly in every
32.768ms, and a valid Vsync must have a frequency greater than
40.7Hz, a valid Vsync pulse will arrive within the 32.768ms window.
Therefore, the user should read the Hsync Frequency Register every
32.768ms to determine the presence of Hsync and/or Vsync pulses.
These two bits are programmed to adjust the DCLK output phase.
Each increment adds approximately 2 to 3ns delay to the DCLK
output.
These two bits together with MUL[7:4] and VRS[7:4] in CGM’s PLL
programming register determine the frequencies of the internal
generated free-running signals for output to HOUT, VOUT, DE, and
DCLK pins, when the SOUT bit is set in the sync processor I/O control
register. These two bits determine the prescaler of PLL reference
clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2;
for other values, the prescaler is 3. Reset clears these bits, setting a
default horizontal frequency of 31.25kHz and a vertical frequency of
60Hz, a video mode of 640×480. (See
Module
VRS[7:4]
3
3
6
9
(CGM).)
Frequency
31.45kHz
37.87kHz
48.37kHz
64.32kHz
HOUT
Sync Processor
Frequency
59.91Hz
60.31Hz
60.31Hz
60.00Hz
VOUT
Frequency
108MHz
24MHz
40MHz
64MHz
DCLK
Section 8. Clock Generator
SXGA 1280 × 1024
SVGA 800 × 600
DE Video Mode
XGA 1024 × 768
VGA 640 × 480
System Operation
Sync Processor
Technical Data
229