HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 37

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 52.
Default values are highlighted.
Table 53.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7 to 6
5 to 4
3 to 1
0
Bit
7 to 6
5 to 4
3 to 1
0
Symbol
-
ADC_MODE[1:0]
-
ADC_PD
Symbol
-
ADC_MODE[1:0]
-
ADC_PD
ADCA_0_Ctrl (address 0890h)
ADCB_0_Ctrl (address 0891h)
-
R/W
-
R/W
Access
-
R/W
Access
-
R/W
All information provided in this document is subject to legal disclaimers.
Value
00
00 (reset)
01
10
11
000
0
1
Value
00
00 (reset)
01
10
11
000
0
1
Rev. 5 — 9 February 2011
Description
not used
defines input type of JESD204A unit:
not used
ADC power-down control:
Description
not used
defines input type of JESD204A unit
not used
ADC power-down control:
ADC output is connected to the JESD204A input
not used
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
ADC is operational
ADC is in Power-down mode
ADC output is connected to the JESD204A input
not used
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
ADC is operational
ADC is in Power-down mode
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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