HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 33

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 33.
Default values are highlighted.
Table 34.
Default values are highlighted.
Table 35.
Default values are highlighted.
Table 36.
Default values are highlighted.
Table 37.
Default values are highlighted.
Table 38.
Default values are highlighted.
Table 39.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7
6 to 0
Bit
7 to 0
Bit
7 to 2
1 to 0
Bit
7 to 0
Bit
7 to 4
3 to 0
Bit
7
6 to 1
0
Bit
7 to 3
2 to 0
Symbol
-
LSB_INIT[6:0]
Symbol
MSB_INIT[7:0]
Symbol
-
PRBS_TYPE[1:0]
Symbol
DID[7:0]
Symbol
-
BID[3:0]
Symbol
SCR
-
L
Symbol
-
F[2:0]
Ser_ScramblerA (address 0809h)
Ser_ScramblerB (address 080Ah)
Ser_PRBS_Ctrl (address 080Bh)
Cfg_0_DID (address 0820h)
Cfg_1_BID (address 0821h)
Cfg_3_SCR_L (address 0822h)
Cfg_4_F (address 0823h)
R/W
-
R/W
R/W
-
-
R/W
Access
-
R/W
Access
Access
Access
R
Access
-
Access
R/W
R/W
Access
All information provided in this document is subject to legal disclaimers.
000000
000000
Value
0
0000000
Value
11111111
Value
00 (reset)
01
10
11
Value
11101101 defines the device (= link) identification number
Value
0000
1010
Value
0
0
Value
00000
001
Rev. 5 — 9 February 2011
Description
not used
defines the initialization vector for the scrambler polynomial
(lower)
Description
defines the initialization vector for the scrambler polynomial
(upper)
Description
not used
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
Description
Description
not used
defines the bank ID – extension to DID
Description
scrambling enabled
not used
defines the number of lanes per converter device, minus 1
Description
not used
defines the number of octets per frame, minus 1
PRBS-7
PRBS-7
PRBS-23
PRBS-31
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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