HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 28

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 18.
Default values are highlighted.
Table 19.
Default values are highlighted.
Table 20.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7 to 2 -
1
0
Bit
7
6 to 2 -
1 to 0 PD[1:0]
Bit
7 to 5 -
4
3
2
1
0
Symbol
ADCB
ADCA
Symbol
SW_RST
Symbol
SE_SEL
DIFF_SE
-
CLKDIV2_SEL
DCS_EN
Register Channel index (address 0003h)
Register Reset and Power-down mode (address 0005h)
Register Clock (address 0006h)
11.6.3.1 ADC control registers
11.6.3 Register description
Access
-
R/W
R/W
Access
R/W
-
R/W
Access
-
R/W
R/W
-
R/W
R/W
Value
111111
0
1
0
1
Value
0
1
00000
00
01
10
11
Value
000
0
1
0
1
0
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
Description
not used
ADC B gets the next SPI command:
ADC A gets the next SPI command:
Description
reset digital part:
not used
Power-down mode:
Description
not used
select SE clock input pin:
differential/single-ended clock input select:
not used
select clock input divider by 2:
duty cycle stabilizer enable:
ADC B not selected
ADC B selected
ADC A not selected
ADC A selected
no reset
performs a reset of the digital part
normal (power-up)
full power-down
sleep
normal (power-up)
select CLKM input
select CLKP input
fully differential
single-ended
disable
active
disable
active
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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