HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 27

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

Table 17.
[1]
Address
(hex)
0826
0827
0828
0829
082C
082D
084C
084D
0870
0871
0890
0891
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
Register name
Cfg_7_CS_N
Cfg_8_Np
Cfg_9_S
Cfg_10_HD_CF
Cfg_01_2_LID
Cfg_02_2_LID
Cfg01_13_FCHK R
Cfg02_13_FCHK R
Lane0_0_Ctrl
Lane1_0_Ctrl
ADCA_0_Ctrl
ADCB_0_Ctrl
Register allocation map
Access
R/W*
R/W
R/W*
R/W*
R/W*
R/W*
R/W
R/W
R/W
R/W
[1]
…continued
Bit 7
HD
0
0
0
0
0
0
0
0
0
SCR_IN_
SCR_IN_
MODE
MODE
CS[0]
Bit 6
0
0
0
0
0
0
0
LANE_MODE[1:0]
LANE_MODE[1:0]
Bit 5
ADC_MODE[1:0]
ADC_MODE[1:0]
0
0
0
0
0
0
Bit 4
0
0
0
Bit definition
FCHK[7:0]
FCHK[7:0]
Bit 3
0
0
0
0
0
0
LANE_
LANE_
Bit 2
POL
POL
LID[4:0]
LID[4:0]
NP[4:0]
0
0
0
0
N[3:0]
LANE_CLK_
LANE_CLK_
POS_EDGE
POS_EDGE
Bit 1
0
0
0
CF[1:0]
LANE_PD
LANE_PD
ADC_PD
ADC_PD
Bit 0
S
Default
(bin)
0100 0100
0000 1111
0000 0000
0000 0000
0001 1011
0001 1100
0000 0000
0000 0000
0000 0001
0000 0000
0000 0001
0000 0000