HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 29

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 21.
Default values are highlighted.
Table 22.
Default values are highlighted.
Table 23.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7 to 4 -
3
2 to 0 INTREF[2:0]
Register Offset
Decimal
+31
...
0
...
32
Bit
7 to 3 -
2 to 0 TESTPAT_1[2:0]
Symbol
INTREF_EN
Symbol
Register Vref (address 0008h)
Digital Offset adjustment (address 0013h)
Register Test pattern 1 (address 0014h)
Access
-
R/W
R/W
Access
-
R/W
DIG_OFFSET[5:0]
011111
...
000000
...
100000
0000
Value
0
1
000
001
010
011
100
101
110
111
Value
00000
000
001
010
011
100
101
110
111
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
Description
not used
enable internal programmable VREF mode:
programmable internal reference:
Description
not used
digital test pattern:
disable
active
0 dB (FS=2 V)
1 dB (FS=1.78 V)
2 dB (FS=1.59 V)
3 dB (FS=1.42 V)
4 dB (FS=1.26 V)
5 dB (FS=1.12 V)
6 dB (FS=1 V)
not used
off
mid-scale
 FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
+31 LSB
...
0
...
32 LSB
© NXP B.V. 2011. All rights reserved.
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