HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 30

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 24.
Default values are highlighted.
Table 25.
Default values are highlighted.
Table 26.
Default values are highlighted.
Table 27.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7 to 0
Bit
7 to 2 TESTPAT_3[5:0]
1 to 0 -
Bit
7
6 to 4 RESERVED[2:0]
3 to 2 -
1
0
Bit
7
6 to 4 -
3
2 to 0 -
Symbol
Symbol
RXSYNC_ERROR
POR_TST
RESERVED
Symbol
SW_RST
FSM_SW_RST
TESTPAT_2[13:6]
Symbol
Register Test pattern 2 (address 0015h)
Register Test pattern 3 (address 0016h)
Ser_Status (address 0801h)
Ser_Reset (address 0802h)
11.6.4 JESD204A digital control registers
Access
R/W
-
Access
R
-
-
R
-
Access
R/W
-
R/W
-
Access
R/W
Value
000000
00
Value
0
100
00
0
0
Value
0
000
0
000
Value
00000000 custom digital test pattern (bit 13 to 6)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
Description
custom digital test pattern (bit 5 to 0)
not used
Description
set to 1 when a synchronization error occurs
reserved
not used
power-on-reset
reserved
Description
initiates a software reset of the JESD204A unit
not used
initiates a software reset of the internal state machine of
JESD204A unit
not used
Description
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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